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Side-channel Attack Standard Evaluation Board |
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| Overview |
The Side-channel Attack Standard Evaluation Board (SASEBO-G) is an FPGA board specifically
designed to develop standard evaluation schemes to secure the cryptographic module against
physical attacks. The SASEBO-G version board incorporates a Xilinx FPGA. Figure above is a
photograph of the SASEBO-G. The basic features of the SASEBO-G are as follows:
* 230 mm x 180 mm x 1.6 mm, FR-4, eight layers.
* Two Xilinx Virtex-II Pro series FPGAs
- Cryptographic FPGA: xc2vp7-fg456-5
- Control FPGA: xc2vp30-fg676-5
These FPGAs are connected through a 16-bit bidirectional data bus and a 16-bit address bus,
controlled by four signals: RD, WT, RESET, and CLOCK.
* Two on-board oscillators provide each FPGA with clock signals at the same frequency of 24
MHz. External clock inputs are also supported.
* External power source supplies on-board power regulators and the FPGAs with 3.3 V. The
power regulators convert the 3.3-V input into 2.5 V, 1.8 V, and 1.5 V for the FPGAs. The core
voltage of 1.5 V of the cryptographic FPGA can also be applied directly through an external
power connector.
* Shunt resistors are provided for power measurement of the FPGAs.
* The host PC controls and communicates with the board via RS-232 or USB port.
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| Overview |
The Side-channel Attack Standard Evaluation Board (SASEBO-B) is an FPGA board specifically
designed to develop standard evaluation schemes to secure the cryptographic module against
physical attacks. The SASEBO-B version board incorporates an ALTERA FPGA. Figure above is a
photograph of the SASEBO-B. The basic features of the SASEBO-B are as follows:
* 230 mm x 180 mm x 1.6 mm, FR-4, eight layers.
* Two ALTERA Stratix II series FPGAs
- Cryptographic FPGA: EP2S15F484C5N
- Control FPGA: EP2S30F672C5N
These FPGAs are connected through a 16-bit bidirectional data bus and a 16-bit address
signal, controlled by four signals: RD, WR, RESET, and CLOCK.
* A 24-MHz oscillator is provided for each FPGA. External clock input is supported.
* Power regulators supply FPGA voltages with 3.3-V input. The core voltage of the
cryptographic FPGA can be applied directly through an external power connector.
* Shunt resistance is provided for power measurement of the FPGAs.
* RS-232 and USB ports for communicating with the host PC.
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 Technical Documents |
| Please download the Data,Manual or a technical documentation of SASEBO from the following link. |
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'SASEBO' Web site |
URL : http://www.rcis.aist.go.jp/special/SASEBO/index-en.html
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'SASEBO-G' Document |
URL : http://www.rcis.aist.go.jp/special/SASEBO/SASEBO-G-en.html
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'SASEBO-B' Document |
URL : http://www.rcis.aist.go.jp/special/SASEBO/SASEBO-B-en.html
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| Sales system |
The SASEBO board becomes the build-to-order manufacturing.
On the appointed date of delivery after the ordering, please refer to follows. |
| Contact Us |
| E-mail:tdc_se@toppan.co.jp |
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