Introduction |
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It is high-speed Viterbi decoder core being developed for PRML(Partial Response Maximum Likelihood), which is widely used in HDD read channel signal processing. Based on our original ACS/pass memory algorithm, this architecture has achieved both of small-size and low-latency at the same time.
Moreover, it is also designed to support change of degree of PR transfer function and various convolutional codes.
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Features |
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Original oop erasure algorithm to decrease computational complexity of ACS loop |
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Parameterizable PR transfer function by setting register
G(D) = PA + PB•D + PC•D2 + PD•D3
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Fully 4 parallel architecture |
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8-State |
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Very low latency |
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Available Two version: Low area or Fast |
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Decode rate MAX2.2Gbps@TSMC 65LP |
Deliverables |
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Verilog RTL Source code |
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FGPA netlist |
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ASIC netlist (need ASIC cell library) |
Performance @ TSMC 65LP |
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Low area version |
Fast version |
| Number of gate |
206Kgate |
285Kgate |
| Operation frequency |
500MHz |
555MHz |
| Latency |
56sample |
64sample |
| Decode rate |
2Gbps |
2.2Gbps |
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Experience |
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Successfully adopted in ASIC |
Applications |
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Hard disk drive |
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Optical disk drive |
Interface |
| Type |
Name |
Description |
| Input |
ICLK |
clock |
| IXRST |
Asynchronous reset |
| IDATA0[n-1:0] |
Input Data at sample t |
| IDATA1[n-1:0] |
Input Data at sample t-1 |
| IDATA2[n-1:0] |
Input Data at sample t-2 |
| IDATA3[n-1:0] |
Input Data at sample t-3 |
| IPR_A[m-1:0] |
PR transfer function A |
| IPR_B[m-1:0] |
PR transfer function B |
| IPR_C[m-1:0] |
PR transfer function C |
| IPR_D[m-1:0] |
PR transfer function D |
| Output |
ODATA[3:0] |
Viterbi decode result |
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Customize
The following customization are possible. |
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Change PR transfer function |
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Data dependent noise prediction (below figure) |
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Soft output viterbi algorithm |
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Add signal distortion compensation |
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Support various convolutional code |
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The content of the description might change without a previous notice for the improvement |
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Contact and Ordering Information tdc_se@toppan.co.jp |