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| To IP Libraries top | High-speed Viterbi Decoder
 
*High-speed Viterbi Decoder

* Introduction
  It is high-speed Viterbi decoder core being developed for PRML(Partial Response Maximum Likelihood), which is widely used in HDD read channel signal processing. Based on our original ACS/pass memory algorithm, this architecture has achieved both of small-size and low-latency at the same time. Moreover, it is also designed to support change of degree of PR transfer function and various convolutional codes.
* Features
Original oop erasure algorithm to decrease computational complexity of ACS loop
Parameterizable PR transfer function by setting register
   G(D) = PA + PB•D + PC•D2 + PD•D3
Fully 4 parallel architecture
8-State
Very low latency
Available Two version: Low area or Fast
Decode rate MAX2.2Gbps@TSMC 65LP
* Deliverables
Verilog RTL Source code
FGPA netlist
ASIC netlist (need ASIC cell library)
* Performance @ TSMC 65LP
  Low area version Fast version
Number of gate 206Kgate 285Kgate
Operation frequency 500MHz 555MHz
Latency 56sample 64sample
Decode rate 2Gbps 2.2Gbps
* Experience
Successfully adopted in ASIC
* Applications
Hard disk drive
Optical disk drive
* Interface
Type   Name   Description
Input   ICLK   clock
  IXRST   Asynchronous reset
  IDATA0[n-1:0]   Input Data at sample t
  IDATA1[n-1:0]   Input Data at sample t-1
  IDATA2[n-1:0]   Input Data at sample t-2
  IDATA3[n-1:0]   Input Data at sample t-3
  IPR_A[m-1:0]   PR transfer function A
  IPR_B[m-1:0]   PR transfer function B
  IPR_C[m-1:0]   PR transfer function C
  IPR_D[m-1:0]   PR transfer function D
  Output   ODATA[3:0]   Viterbi decode result
* Customize
  The following customization are possible.
Change PR transfer function
Data dependent noise prediction (below figure)
Soft output viterbi algorithm
Add signal distortion compensation
Support various convolutional code
noise prediction graph
The content of the description might change without a previous notice for the improvement
Contact and Ordering Information tdc_se@toppan.co.jp
 
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