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Library Development |
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We provide prompt development of basic standard cells and I/O cells used in system LSI, suited to the
requirements of the target LSI. |
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LV-TTL, LV-CMOS compatible
Power supply voltages in accordance with
JEDEC specifications
(3.3V, 2.5V, 1.8V)
PDC, mobile uses 2.85V, etc.
Drive capability switching type
Through rate control type |
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PCI interfaces
33MHz, 5V-PCI, 3.3V-PCI
3.3V / 5V switching
66MHz, 3.3V-PCI
PCI-X
CARD BUS interface |
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IEEE compliant interfaces
MII, GMII, TBI (Ethernet: IEEE 802.3)
IEEE 1394 interface between PHY - LINK
IEEE 1284 parallel port interface |
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Intel MPU interface
GTL+
LP-GTL+ |
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I2C interface |
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ATA-33, ATA-66 |
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LV-pECL (receiver) |
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SSTL2, HSTL
Compliant with JEDEC specifications
SSTL2 class 1, 2 for DDR200 use
SSTL2 class 1 for DDR266 use
HSTL (200MHz) class 1, 2, 3, 4 |
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USB 1.1 interface
Full Speed, Low Speed for HOST |
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LVDS |
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Serial-ATA
Operating frequency 1.5GHz |
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Package-oriented development
Available Package type: Standard peripheral PAD,
FCBGA,CUP, BOAC, or PADs placed in core area. |
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Power supply management
In accordance with product specifications, we provide multiple power supplies, power supply fold-back, function switching, leakage current prevention, and others, in accordance to the
customer's specific requirements. |
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Validation by taking into
account the transmission path and package condition
In accordance with the customer's requirements, we confirm and verify the characteristics of the transmission paths provided, including the package information. |
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High-speed serial differential
buffer design
-Precise control over Duty, CrossPoint
-Through rate control
-Bias voltage optimization
-For PHY modules, we provide complete module design including PLL design, taking into account
the jitter specification. |
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